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2005
IEEE

An architectural level design methodology for embedded face detection

10 years 3 months ago
An architectural level design methodology for embedded face detection
Face detection and recognition research has attracted great attention in recent years. Automatic face detection has great potential in a large array of application areas, including banking and security system access control, video surveillance, and multimedia information retrieval. In this paper, we discuss an architectural level design methodology for implementation of an embedded face detection system on a reconfigurable system on chip. We present models for performance estimation and validate these models with experimental values obtained from implementing our system on an FPGA platform. This modeling approach is shown to be efficient, accurate, and intuitive for designers to work with. Using this approach, we present several design options that trade-off various architectural features. Categories and Subject Descriptors C.3 [Real-time embedded systems] General Terms Design Keywords Design space exploration, face detection, reconfigurable platforms, system-level models.
Vida Kianzad, Sankalita Saha, Jason Schlessman, Ga
Added 24 Jun 2010
Updated 24 Jun 2010
Type Conference
Year 2005
Where CODES
Authors Vida Kianzad, Sankalita Saha, Jason Schlessman, Gaurav Aggarwal, Shuvra S. Bhattacharyya, Wayne Wolf, Rama Chellappa
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