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CODES
2003
IEEE
9 years 3 months ago
Design space minimization with timing and code size optimization for embedded DSP
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...
Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-M...
CODES
2003
IEEE
9 years 3 months ago
RTOS scheduling in transaction level models
the level of abstraction in system design promises to enable faster exploration of the design space at early stages. While scheduling decision for embedded software has great impa...
Haobo Yu, Andreas Gerstlauer, Daniel Gajski
CODES
2003
IEEE
9 years 3 months ago
Virtual synchronization technique with OS modeling for fast and time-accurate cosimulation
Hardware/Software cosimulation is the key process to shorten the design turn around time. We have proposed a novel technique, called virtual synchronization, for fast and time acc...
Youngmin Yi, Dohyung Kim, Soonhoi Ha
CODES
2003
IEEE
9 years 3 months ago
Deriving process networks from weakly dynamic applications in system-level design
We present an approach to the automatic derivation of executable Process Network specifications from Weakly Dynamic Applications. We introduce the notions of Dynamic Single Assig...
Todor Stefanov, Ed F. Deprettere
CODES
2003
IEEE
9 years 3 months ago
A low power scheduler using game theory
In this paper, we describe a new methodology based on game theory for minimizing the average power of a circuit during scheduling in behavioral synthesis. The problem of schedulin...
N. Ranganathan, Ashok K. Murugavel
CODES
2003
IEEE
9 years 3 months ago
Design optimization of mixed time/event-triggered distributed embedded systems
Distributed embedded systems implemented with mixed, eventtriggered and time-triggered task sets, which communicate over bus protocols consisting of both static and dynamic phases...
Traian Pop, Petru Eles, Zebo Peng
CODES
2003
IEEE
9 years 3 months ago
Programmers' views of SoCs
System-on-chip (SoC) designs have the potential to change the way we organize computation. This potential has gone unrealized. Future SoCs will have multiple heterogeneous process...
JoAnn M. Paul
CODES
2003
IEEE
9 years 3 months ago
A fast parallel reed-solomon decoder on a reconfigurable architecture
This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targ...
Arezou Koohi, Nader Bagherzadeh, Chengzi Pan
CODES
2003
IEEE
9 years 3 months ago
Hardware support for real-time operating systems
The growing complexity of embedded applications and pressure on time-to-market has resulted in the increasing use of embedded real-time operating systems. Unfortunately, RTOSes ca...
Paul Kohout, Brinda Ganesh, Bruce L. Jacob
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