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    ISCAS
    1999
    IEEE
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    An area-efficient analog VLSI architecture for state-parallel Viterbi decoding

    13 years 8 months ago
    An area-efficient analog VLSI architecture for state-parallel Viterbi decoding
    Download  www.isn.ucsd.edu
    Kai He, Gert Cauwenberghs
    claim paper
    Added 03 Aug 2010
    Updated 03 Aug 2010
    Type Conference
    Year 1999
    Where ISCAS
    Authors Kai He, Gert Cauwenberghs
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