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ISCAS
1999
IEEE
102views Hardware» more  ISCAS 1999»
9 years 23 days ago
An asynchronous data recovery/retransmission technique with foreground DLL calibration
S. Nagavarapu, J. Yan, E. K. F. Lee, Randall L. Ge...
ISCAS
1999
IEEE
126views Hardware» more  ISCAS 1999»
9 years 23 days ago
Applications of clone circuits to issues in physical-design
In a companion paper of this session [1] we formally defined the notion of equivalence classes of circuits which are physical clones of an existing benchmark seed circuit created ...
Michael D. Hutton, Jonathan Rose
ISCAS
1999
IEEE
94views Hardware» more  ISCAS 1999»
9 years 23 days ago
Correct diagnosis of almost all faulty units in a multiprocessor system
Krishnaiyan Thulasiraman, Anindya Das, Kaiyuan Hua...
ISCAS
1999
IEEE
99views Hardware» more  ISCAS 1999»
9 years 23 days ago
CMOS gate modeling based on equivalent inverter
A method for modeling complex CMOS gates by the reduction of each gate to an effective equivalent inverter is introduced. The conducting and parasitic behavior of parallel and ser...
Alexander Chatzigeorgiou, Spiridon Nikolaidis, Ioa...
ISCAS
1999
IEEE
121views Hardware» more  ISCAS 1999»
9 years 23 days ago
The linear time-varying approach applied to a first-order dynamic translinear filter
Dynamic translinear (DTL) circuits use the exponential inputoutput relation of the transistor as a primitive for the synthesis of electronic circuits. As a consequence the analysi...
F. C. M. Kuijstermans, F. M. Diepstraten, Wouter A...
ISCAS
1999
IEEE
116views Hardware» more  ISCAS 1999»
9 years 23 days ago
Analysis of noise in higher-order translinear filters
Noise analysis of higher-order translinear filters cannot be established through straight-forward extension of analysis techniques for first-order TL filters, due to the presence n...
Michiel H. L. Kouwenhoven, J. Mulder, Wouter A. Se...
ISCAS
1999
IEEE
88views Hardware» more  ISCAS 1999»
9 years 23 days ago
Signal waveform characterization in RLC trees
- Closed form solutions for the 50% delay, rise time, overshoot characteristics, and settling time of signals in an RLC tree are presented. These solutions have the same accuracy c...
Yehea I. Ismail, Eby G. Friedman, José Luis...
ISCAS
1999
IEEE
106views Hardware» more  ISCAS 1999»
9 years 23 days ago
Repeater insertion in RLC lines for minimum propagation delay
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
Yehea I. Ismail, Eby G. Friedman
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