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8

ASYNC
2000
IEEE

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Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL

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Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL

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Ivan Blunno, Luciano Lavagno

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Added	30 Jul 2010
Updated	30 Jul 2010
Type	Conference
Year	2000
Where	ASYNC
Authors	Ivan Blunno, Luciano Lavagno

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