ASYNC
2000
IEEE
13 years 9 months ago
2000
IEEE
ASYNC
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper we describe a complete design methodology for a globally asynchronous onchip communication network connecting both locally-synchronous and asynchronous modules. Sync...
ASYNC
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper brings together a selection of creative circuit designs and ideas that Charles Molnar devised while working at Sun Microsystems Laboratories. The circuits offer fast im...
ASYNC
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper introduces several new asynchronous pipeline designs which offer high throughput as well as low latency. The designs target dynamic datapaths, both dualrail as well as ...
ASYNC
2000
IEEE
13 years 9 months ago
2000
IEEE
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
ASYNC
2000
IEEE
13 years 9 months ago
2000
IEEE
New design technologies rely on truly reusable IP blocks with simple means of assembly. Asynchronous methodologies could be a promising option to implement these requirements. Pro...
ASYNC
2000
IEEE
13 years 9 months ago
2000
IEEE
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
ASYNC
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper presents several new asynchronous FIFO designs. While most existing FIFO’s trade higher throughput for higher latency, our goal is to achieve very low latency while m...
ASYNC
2000
IEEE
13 years 9 months ago
2000
IEEE
ASYNC
2000
IEEE
13 years 9 months ago
2000
IEEE
The following pages contain the final version for a chapter in the book Advances in Concurrency and Hardware Design (ACHD), to be published by Springer-Verlag in 2002. The editor...