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RECONFIG
2008
IEEE

Automatic Construction of Large-Scale Regular Expression Matching Engines on FPGA

10 years 5 months ago
Automatic Construction of Large-Scale Regular Expression Matching Engines on FPGA
—We present algorithms for implementing large-scale regular expression matching (REM) on FPGA. Based on the proposed algorithms, we develop tools that first transform regular expressions into corresponding non-deterministic finite automata (RE-NFA), then convert the RE-NFA into structural VHDL that utilize both logic slices and block memory (BRAM) available on modern FPGA devices. An n-state m-character input regular expression matching engine (REME) can be constructed in O (n × m log2 m) time using O (n × m) memory space, resulting in a circuit that occupies no more than O (n × m) slices on FPGA. A large number of REMEs are placed automatically onto a twodimensional staged pipeline, allowing scalability to hundreds of REMEs with linear area increase, running at over 300 MHz on Xilinx Virtex 4 devices.
Yi-Hua E. Yang, Viktor K. Prasanna
Added 01 Jun 2010
Updated 01 Jun 2010
Type Conference
Year 2008
Where RECONFIG
Authors Yi-Hua E. Yang, Viktor K. Prasanna
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