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FPGA
2016
ACM

Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis

3 years 6 months ago
Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis
Loops are pervasive in numerical programs, so high-level synthesis (HLS) tools use state-of-the-art scheduling techniques to pipeline them efficiently. Still, the run time performance of the resultant FPGA implementation is limited by data dependences between loop iterations. Some of these dependence constraints can be alleviated by rewriting the program according to arithmetic identities (e.g. associativity and distributivity), memory access reductions, and control flow optimizations (e.g. partial loop unrolling). HLS tools cannot safely enable such rewrites by default because they may impact the accuracy of floating-point computations and increase area usage. In this paper, we introduce the first open-source program optimizer for automatically rewriting a given program to optimize latency while controlling for accuracy and area. Our tool, SOAP3, reports a multi-dimensional Pareto frontier that the programmer can use to resolve the trade-off according to their needs. When applied...
Xitong Gao, John Wickerson, George A. Constantinid
Added 03 Apr 2016
Updated 03 Apr 2016
Type Journal
Year 2016
Where FPGA
Authors Xitong Gao, John Wickerson, George A. Constantinides
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