Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

12

ISVLSI
2005
IEEE

favoriteEmaildiscussreport

113views VLSI» more ISVLSI 2005»

Balancing System Level Pipelines with Stage Voltage Scaling

13 years 10 months ago

Balancing System Level Pipelines with Stage Voltage Scaling

Download www.cse.unsw.edu.au

This paper presents an approach to dynamically balance the pipeline by scaling the stage supply voltages. Simulation results show that by such an approach about 50% improvement in throughput and response time, and 11% improvement in power consumption can be achieved with limited memory overhead.

Hui Guo, Sri Parameswaran

Real-time Traffic

ISVLSI 2005 | Limited Memory Overhead | Power Consumption | Stage Supply Voltages |

claim paper

Related Content

» Reducing pipeline energy demands with local DVS and dynamic retiming

» Razor A LowPower Pipeline Based on CircuitLevel Timing Speculation

» The StageNet fabric for constructing resilient multicore systems

» StageNetSlice a reconfigurable microarchitecture building block for resilient CMP systems

» ApplicationDriven Processor Design Exploration for PowerPerformance Tradeoff Analysis

» Pomegranate a fully scalable graphics architecture

» StageNet A Reconfigurable Fabric for Constructing Dependable CMPs

» Dynamic task set partitioning based on balancing memory requirements to reduce power consu...

» Communication speed selection for embedded systems with networked voltagescalable processo...

Post Info
More Details (n/a)

Added	25 Jun 2010
Updated	25 Jun 2010
Type	Conference
Year	2005
Where	ISVLSI
Authors	Hui Guo, Sri Parameswaran

Comments (0)