The Case for Analog Circuit Verification

The traditional approach to validate analog circuits is to utilize extensive SPICElevel simulations. The main challenge of this approach is knowing when all important corner cases have been simulated. A new alternative is to utilize formal verification techniques. This paper utilizes a simple example to illustrate the potential flaws of a simulation-only based validation methodology and the potential benefits of formal verification of analog circuits. Key words: Analog circuits, formal verification, hybrid Petri nets

• Type: Journal
• Year: 2006
• Where: ENTCS
• Authors: Chris J. Myers, Reid R. Harrison, David Walter, Nicholas Seegmiller, Scott Little
• Keywords: Analog Circuits, ENTCS 2006, Formal Verification, Formal Verification Techniques