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ICSE
2009
IEEE-ACM
8 years 2 months ago
Model checking flight control systems: The Airbus experience
This paper presents experiments realized by Airbus on model checking a safety critical system, lessons learnt and ways forward to extend the industrial use of formal verification ...
Thomas Bochot, Pierre Virelizier, Hél&egrav...
SAFECOMP
2010
Springer
8 years 2 months ago
Experiences in Applying Formal Verification in Robotics
Formal verification efforts in the area of robotics are still comparatively scarce. In this paper we report on our experiences with one such effort, which was concerned with design...
Dennis Walter, Holger Täubig, Christoph L&uum...
JSA
2008
131views more  JSA 2008»
8 years 3 months ago
Formal verification of ASMs using MDGs
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...
Amjad Gawanmeh, Sofiène Tahar, Kirsten Wint...
JISE
1998
106views more  JISE 1998»
8 years 4 months ago
Control / Data-Flow Analysis for VHDL Semantic Extraction
straction reduces the number of states necessary to perform formal verification while maintaining the functionality of the original model with respect to ifications to be verified....
Yee-Wing Hsieh, Steven P. Levitan
FMSD
2002
128views more  FMSD 2002»
8 years 4 months ago
Combining Software and Hardware Verification Techniques
Combining verification methods developed separately for software and hardware is motivated by the industry's need for a technology that would make formal verification of reali...
Robert P. Kurshan, Vladimir Levin, Marius Minea, D...
JAR
2008
101views more  JAR 2008»
8 years 4 months ago
Tilting at Windmills with Coq: Formal Verification of a Compilation Algorithm for Parallel Moves
This article describes the formal verification of a compilation algorithm that transforms parallel moves (parallel assignments between variables) into a semanticallyequivalent sequ...
Laurence Rideau, Bernard P. Serpette, Xavier Leroy
ENTCS
2006
130views more  ENTCS 2006»
8 years 4 months ago
LSC Verification for UML Models with Unbounded Creation and Destruction
The approaches to automatic formal verification of UML models known up to now require a finite bound on the number of objects existing at each point in time. In [4] we have observ...
Bernd Westphal
ENTCS
2006
131views more  ENTCS 2006»
8 years 4 months ago
The Case for Analog Circuit Verification
The traditional approach to validate analog circuits is to utilize extensive SPICElevel simulations. The main challenge of this approach is knowing when all important corner cases...
Chris J. Myers, Reid R. Harrison, David Walter, Ni...
CORR
2010
Springer
122views Education» more  CORR 2010»
8 years 4 months ago
Specifying Reusable Components
Reusable software components need well-defined interfaces, rigorously and completely documented features, and a design amenable both to reuse and to formal verification; all these...
Nadia Polikarpova, Carlo A. Furia, Bertrand Meyer
CL
2008
Springer
8 years 4 months ago
Automatic synthesis and verification of real-time embedded software for mobile and ubiquitous systems
Currently available application frameworks that target the automatic design of real-time embedded software are poor in integrating functional and non-functional requirements for m...
Pao-Ann Hsiung, Shang-Wei Lin
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