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On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism

9 years 1 months ago
On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism
—Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated into the SoC to function as an ATE. This paper introduces the reuse of a Network-on-Chip as a test access mechanism. Since the scan-based test is performed on-chip via the NoC at application run-time, it needs to share the NoC bandwidth with other applications. Instead of reserving sufficient NoC bandwidth for the test, the authors propose a novel way to carry out scan-based tests by dynamically pausing and resuming the test data flow to accommodate the fluctuating communication bandwidth available on the NoC. The test stimuli application and test response collection processes are decoupled to meet the global timing constraint. The many-core processor, IIP and the NoC have been implemented in synthesizable VHDL. Simulation results show the correct application of standard structural test patterns to the process...
Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen
Added 06 Dec 2010
Updated 06 Dec 2010
Type Conference
Year 2010
Where DSD
Authors Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen
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