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DAC
2006
ACM

Circuit simulation based obstacle-aware Steiner routing

10 years 1 months ago
Circuit simulation based obstacle-aware Steiner routing
Steiner routing is a fundamental yet NP-hard problem in VLSI design and other research fields. In this paper, we propose to model the routing graph by an RC network with routing terminals as input ports and Hanan nodes as output ports. We show that the faster an output reaches its peak, the higher the possibility for the correspondent Hanan node to be a Steiner point. Iteratively adding one or multiple selected Steiner points to build and improve Steiner trees leads to 1-cktSteiner and Blocked-cktSteiner (in short, B-cktSteiner) algorithms, respectively. When there are no routing obstacles, 1-cktSteiner obtains similar wirelength compared with the best existing algorithm FastSteiner. Both are less than 1% worse than the exact solution, but 1-cktSteiner is up to
Yiyu Shi, Paul Mesa, Hao Yu, Lei He
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2006
Where DAC
Authors Yiyu Shi, Paul Mesa, Hao Yu, Lei He
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