A timing-constrained simultaneous global routing algorithm

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A timing-constrained simultaneous global routing algorithm
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provides a general framework that may use any single-net routing algorithm and any delay model in global routing. It is based on the observation that there are several routing topology flexibilities that can be exploited for congestion reduction under timing constraints. These flexibilities are expressed through the concepts of a soft edge and a slideable Steiner node. Starting with an initial solution where timing driven routing is performed on each net without regard to congestion constraints, this algorithm hierarchically bisects a routing region and assigns soft edges to the cell boundaries along the bisector line. The assignment is achieved through a network flow formulation so that the amount of timing slack used to reduce congestions is adaptive to the congestion distributions. Finally, a timing-constrained...
Jiang Hu, Sachin S. Sapatnekar
Added 23 Dec 2010
Updated 23 Dec 2010
Type Journal
Year 2002
Where TCAD
Authors Jiang Hu, Sachin S. Sapatnekar
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