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PAIRING
2010
Springer

Compact Hardware for Computing the Tate Pairing over 128-Bit-Security Supersingular Curves

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Compact Hardware for Computing the Tate Pairing over 128-Bit-Security Supersingular Curves
This paper presents a novel method for designing compact yet efficient hardware implementations of the Tate pairing over supersingular curves in small characteristic. Since such curves are usually restricted to lower levels of security because of their bounded embedding degree, aiming for the recommended security of 128 bits implies considering them over very large finite fields. We however manage to mitigate this effect by considering curves over field extensions of moderately-composite degree, hence taking advantage of a much easier tower field arithmetic. This technique of course lowers the security on the curves, which are then vulnerable to Weil descent attacks, but a careful analysis allows us to maintain their security above the 128-bit threshold. As a proof of concept of the proposed method, we detail an FPGA accelerator for computing the Tate pairing on a supersingular curve over F35·97 , which satisfies the 128-bit security target. On a mid-range Xilinx Virtex-4 FPGA, ...
Nicolas Estibals
Added 29 Jan 2011
Updated 29 Jan 2011
Type Journal
Year 2010
Where PAIRING
Authors Nicolas Estibals
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