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2003
ACM

Compile-time dynamic voltage scaling settings: opportunities and limits

9 years 2 months ago
Compile-time dynamic voltage scaling settings: opportunities and limits
With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-time powermanagement techniques, dynamic voltage scaling (DVS) has emerged as an important approach, with the ability to provide significant power savings. DVS exploits the ability to control the power consumption by varying a processor’s supply voltage (V) and clock frequency (f). DVS controls energy by scheduling different parts of the computation to different (V, f) pairs; the goal is to minimize energy while meeting performance needs. Although processors like the Intel XScale and Transmeta Crusoe allow software DVS control, such control has thus far largely been used at the process/task level under operating system control. This is mainly because the energy and time overhead for switching DVS modes is considered too large and difficult to manage within a single program. In this paper we explore the opp...
Fen Xie, Margaret Martonosi, Sharad Malik
Added 05 Jul 2010
Updated 05 Jul 2010
Type Conference
Year 2003
Where PLDI
Authors Fen Xie, Margaret Martonosi, Sharad Malik
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