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EMSOFT
2001
Springer

Compiler Optimizations for Adaptive EPIC Processors

13 years 8 months ago
Compiler Optimizations for Adaptive EPIC Processors
Abstract. Advances in VLSI technology have lead to a tremendous increase in the density and number of devices that can be manufactured in a single microchip. One of the interesting ways in which this silicon may be used is to leave portions of it uncommitted and re-programmable depending on an applications needs. In an earlier paper, we proposed a machine architecture for achieving this reconfigurability and compilation issues that such an architecture will face. In this paper, we will elaborate on the compiler optimization issues involved. In particular, we will outline a framework for code partitioning, instruction synthesis, configuration selection, resource allocation, and instruction scheduling. Partitioning is the problem of identifying code sections that may benefit by mapping them on to the programmable logic resources. The instruction synthesis phase generates suitable implementations for the candidates partitions and updates the machine description database with the new in...
Krishna V. Palem, Surendranath Talla, Weng-Fai Won
Added 28 Jul 2010
Updated 28 Jul 2010
Type Conference
Year 2001
Where EMSOFT
Authors Krishna V. Palem, Surendranath Talla, Weng-Fai Wong
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