Sciweavers

Share
ICMCS
2006
IEEE

Complexity Analysis of H.264 Decoder for FPGA Design

10 years 1 months ago
Complexity Analysis of H.264 Decoder for FPGA Design
— A major challenge in the design of any real time system is the proper selection of implementation and platform alternatives. In this paper, a suitable FPGA-based design of the H.264 decoder is presented. Since H.264 standard only specifies the syntax and semantics of the video stream and not the video codec itself, the selection process may be directed based upon the temporal complexity of different parts of the decoder. Here, we present the process flow of these parts using basic algebraic operators. The analysis of the required logic elements to implement the decoder, on various platforms, is presented. H.264 decoder; decoding block; baseline profile
Tuomas Lindroth, Nastooh Avessta, Jukka Teuhola, T
Added 11 Jun 2010
Updated 11 Jun 2010
Type Conference
Year 2006
Where ICMCS
Authors Tuomas Lindroth, Nastooh Avessta, Jukka Teuhola, Tiberiu Seceleanu
Comments (0)
books