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EUROSYS
2010
ACM

A Comprehensive Scheduler for Asymmetric Multicore Systems

14 years 21 days ago
A Comprehensive Scheduler for Asymmetric Multicore Systems
Symmetric-ISA (instruction set architecture) asymmetricperformance multicore processors were shown to deliver higher performance per watt and area for codes with diverse architectural requirements, and so it is likely that future multicore processors will combine a few fast cores characterized by complex pipelines, high clock frequency, high area requirements and power consumption, and many slow ones, characterized by simple pipelines, low clock frequency, low area requirements and power consumption. Asymmetric multicore processors (AMP) derive their efficiency from core specialization. Efficiency specialization ensures that fast cores are used for “CPU-intensive” applications, which efficiently utilize these cores’ “expensive” features, while slow cores would be used for “memory-intensive” applications, which utilize fast cores inefficiently. TLP (thread-level parallelism) specialization ensures that fast cores are used to accelerate sequential phases of parallel ap...
Juan Carlos Saez, Manuel Prieto Matias, Alexandra
Added 10 Mar 2010
Updated 10 Mar 2010
Type Conference
Year 2010
Where EUROSYS
Authors Juan Carlos Saez, Manuel Prieto Matias, Alexandra Fedorova, Sergey Blagodurov
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