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JISE
1998

Control / Data-Flow Analysis for VHDL Semantic Extraction

9 years 6 months ago
Control / Data-Flow Analysis for VHDL Semantic Extraction
straction reduces the number of states necessary to perform formal verification while maintaining the functionality of the original model with respect to ifications to be verified. However, in order to perform model abstraction, we must extract the semantics of the model itself. In this paper, we describe a method for ng VHDL semantics for model abstraction to improve the performance of formal verification tools such as COSPAN.
Yee-Wing Hsieh, Steven P. Levitan
Added 22 Dec 2010
Updated 22 Dec 2010
Type Journal
Year 1998
Where JISE
Authors Yee-Wing Hsieh, Steven P. Levitan
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