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DAMON
2008
Springer

Data partitioning on chip multiprocessors

8 years 4 months ago
Data partitioning on chip multiprocessors
Partitioning is a key database task. In this paper we explore partitioning performance on a chip multiprocessor (CMP) that provides a relatively high degree of on-chip thread-level parallelism. It is therefore important to implement the partitioning algorithm to take advantage of the CMP's parallel execution resources. We identify the coordination of writing partition output as the main challenge in a parallel partitioning implementation and evaluate four techniques for enabling parallel partitioning. We confirm previous work in single threaded partitioning that finds L2 cache misses and translation lookaside buffer misses to be important performance issues, but we now add the management of concurrent threads to this analysis.
John Cieslewicz, Kenneth A. Ross
Added 19 Oct 2010
Updated 19 Oct 2010
Type Conference
Year 2008
Where DAMON
Authors John Cieslewicz, Kenneth A. Ross
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