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ARITH
2009
IEEE

Datapath Synthesis for Standard-Cell Design

12 years 8 days ago
Datapath Synthesis for Standard-Cell Design
Datapath synthesis for standard-cell design goes through extraction of arithmetic operations from RTL code, high-level arithmetic optimizations and netlist generation. Numerous architectures and optimization strategies exist that result in circuit implementations with very different performance characteristics. This work summarizes the circuit architectures and techniques used in a commercial synthesis tool to optimize cell-based datapath netlists for timing, area and power.
Reto Zimmermann
Added 18 May 2010
Updated 18 May 2010
Type Conference
Year 2009
Where ARITH
Authors Reto Zimmermann
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