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2008

A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors

8 years 5 months ago
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable application-specific instruction set processors (rASIPs) which combine a programmable base processor with a reconfigurable fabric. Although such processors promise to deliver excellent balance between performance and flexibility, their design remains a challenging task. The key to the successful design of a rASIP is combined architecture exploration of all the three major components: the programmable core, the reconfigurable fabric, and the interfaces between these two. This work presents a design flow that supports fast architecture exploration for rASIPs. The design flow is centered around a unified description of an entire rASIP in an Architecture Description Language (ADL). This ADL description facilitates consistent modeling and exploration of all three components of a rASIP through automatic generation of the ...
Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Che
Added 16 Dec 2010
Updated 16 Dec 2010
Type Journal
Year 2008
Where TVLSI
Authors Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, Heinrich Meyr, Gerd Ascheid
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