TVLSI 2008 - PDF Preprint Papers

TVLSI 2008

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TVLSI
2008

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Effective Radii of On-Chip Decoupling Capacitors

13 years 4 months ago

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Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on a die or place...

Mikhail Popovich, Michael Sotman, Avinoam Kolodny,...

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Id	Views	Title	Status

1	207	Effective Radii of On-Chip Decoupling Capacitors	claim
2	197	Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology	claim
3	187	A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors	claim
4	176	A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing	claim
5	169	Energy-Aware Flash Memory Management in Virtual Memory System	claim
6	164	Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication	claim
7	157	Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory	claim
8	153	Characterization of a Novel Nine-Transistor SRAM Cell	claim
9	152	MMV: A Metamodeling Based Microprocessor Validation Environment	claim
10	151	Guest Editorial Special Section on Design Verification and Validation	claim
11	150	Data Memory Subsystem Resilient to Process Variations	claim
12	149	Architectural Modifications to Enhance the Floating-Point Performance of FPGAs	claim
13	144	Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective	claim
14	140	A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions	claim
15	139	Ternary CAM Power and Delay Model: Extensions and Uses	claim
16	135	On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits	claim
17	133	A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance	claim
18	133	Test Data Compression Using Selective Encoding of Scan Slices	claim
19	132	Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware	claim
20	126	Body Bias Voltage Computations for Process and Temperature Compensation	claim
21	124	A Refinement-Based Compositional Reasoning Framework for Pipelined Machine Verification	claim
22	123	Cost-Efficient SHA Hardware Accelerators	claim
23	123	Automatic Constraint Based Test Generation for Behavioral HDL Models	claim
24	121	Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores	claim
25	120	An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors	claim
26	119	Automatic Design of Reconfigurable Domain-Specific Flexible Cores	claim
27	117	Configurable VLSI Architecture for Deblocking Filter in H.264/AVC	claim
28	116	Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs	claim
29	116	GOP-Level Dynamic Thermal Management in MPEG-2 Decoding	claim
30	116	Adaptive Cooling of Integrated Circuits Using Digital Microfluidics	claim
31	115	Outer Loop Pipelining for Application Specific Datapaths in FPGAs	claim
32	112	System Architecture and Implementation of MIMO Sphere Decoders on FPGA	claim
33	111	GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering	claim
34	110	Thermal Switching Error Versus Delay Tradeoffs in Clocked QCA Circuits	claim
35	108	Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel	claim
36	107	Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs	claim
37	107	Novel Probabilistic Combinational Equivalence Checking	claim
38	106	New Non-Volatile Memory Structures for FPGA Architectures	claim
39	106	Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs	claim
40	105	Guest Editorial Special Section on Low-Power Electronics and Design	claim
41	105	Fast Estimation of Timing Yield Bounds for Process Variations	claim
42	105	Robust Concurrent Online Testing of Network-on-Chip-Based SoCs	claim
43	102	A Robust 4-PAM Signaling Scheme for Inter-Chip Links Using Coding in Space	claim
44	99	A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies	claim
45	96	Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors	claim
46	92	Reconfigurable Architecture for Network Flow Analysis	claim
47	90	A Special-Purpose Architecture for Solving the Breakpoint Median Problem	claim
48	89	Scalable Multigigabit Pattern Matching for Packet Inspection	claim
49	89	Test Set Development for Cache Memory in Modern Microprocessors	claim
50	86	Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking	claim
51	85	Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors	claim
52	78	Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime	claim
53	74	Stack Sizing for Optimal Current Drivability in Subthreshold Circuits	claim
54	72	Simulation Bounds for Equivalence Verification of Polynomial Datapaths Using Finite Ring Algebra	claim

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