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2001
IEEE

A design framework to efficiently explore energy-delay tradeoffs

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A design framework to efficiently explore energy-delay tradeoffs
Comprehensive exploration of the design space parameters at the system-level is a crucial task to evaluate architectural tradeoffs accounting for both energy and performance constraints. In this paper, we propose a system-level design methodology for the efficient exploration of the memory architecture from the energy-delay combined perspective. The aim is to find a sub-optimal configuration of the memory hierarchy without performing the exhaustive analysis of the parameters space. The target system architecture includes the processor, separated instruction and data levelone caches, the main memory, and the system buses. The methodology is based on the sensitivity analysis of the optimization function with respect to the tuning parameters of the cache architecture (mainly cache size, block size and associativity). The effectiveness of the proposed methodology has been demonstrated through the design space exploration of a real-world example: a MicroSPARC2-based system running the Medi...
William Fornaciari, Donatella Sciuto, Cristina Sil
Added 23 Aug 2010
Updated 23 Aug 2010
Type Conference
Year 2001
Where CODES
Authors William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
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