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2003
ACM

The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction

9 years 2 months ago
The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction
This paper presents the design and implementation of a compiler algorithm that effectively optimizes programs for energy usage using dynamic voltage scaling (DVS). The algorithm identifies program regions where the CPU can be slowed down with negligible performance loss. It is implemented as a source-to-source level transformation using the SUIF2 compiler infrastructure. Physical measurements on a high-performance laptop show that total system (i.e., laptop) energy savings of up to 28% can be achieved with performance degradation of less than 5% for the SPECfp95 benchmarks. On average, the system energy and energydelay product are reduced by 11% and 9%, respectively, with a performance slowdown of 2%. It was also discovered that the energy usage of the programs using our DVS algorithm is within 6% from the theoretical lower bound. To the best of our knowledge, this is one of the first work that evaluates DVS algorithms by physical measurements. Categories and Subject Descriptors D....
Chung-Hsing Hsu, Ulrich Kremer
Added 05 Jul 2010
Updated 05 Jul 2010
Type Conference
Year 2003
Where PLDI
Authors Chung-Hsing Hsu, Ulrich Kremer
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