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EUROMICRO
1999
IEEE

Design Space Exploration in System Level Synthesis under Memory Constraints

8 years 9 months ago
Design Space Exploration in System Level Synthesis under Memory Constraints
This paper addresses the problem of component selection, task assignment and task scheduling for distributed embedded computer systems. Such systems have a large number of constraints of different nature, such as cost, execution time, memory capacity and limitations on resource usage. Previous approaches have concentrated on a specific class of requirements and thus they limit number of constraints which can be handled in the design process. This results very often in non-feasible or too expensive solutions. The system presented in this paper CLASS (Constraint Logic bAsed System Synthesis) makes it possible to impose different design constraints and thus model the design more realistically. It is also efficient in finding good solutions or, in some cases, optimal solutions for even nontrivial problems.
Radoslaw Szymanek, Krzysztof Kuchcinski
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where EUROMICRO
Authors Radoslaw Szymanek, Krzysztof Kuchcinski
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