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2010
IEEE

A Parallel for Loop Memory Template for a High Level Synthesis Compiler

8 years 9 months ago
A Parallel for Loop Memory Template for a High Level Synthesis Compiler
—We propose a parametrized memory template for applications with parallel for loops. The template’s parameters reflect important trade-offs made during system design. The template is incorporated in our high level synthesis (HLS) compiler, where the template’s parameters are adjusted to the application. The template fits parallel for loops with no loop dependencies and sequential bodies. We found two alternative template implementations using our compiler. In the future, we will develop templates for other types of for loops. These will be added to the compiler and it will identify the template that works best for the application it is compiling. Once a template is selected, the compiler will use design space exploration to select the best combination of template parameters for the targeted hardware and application.
Craig Moore, Wim Meeus, Harald Devos, Dirk Strooba
Added 24 Jan 2011
Updated 24 Jan 2011
Type Journal
Year 2010
Where DSD
Authors Craig Moore, Wim Meeus, Harald Devos, Dirk Stroobandt
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