Sciweavers

Share
FPT
2005
IEEE

Designing an FPGA SoC Using a Standardized IP Block Interface

9 years 9 months ago
Designing an FPGA SoC Using a Standardized IP Block Interface
Designing Systems on-Chip is becoming increasingly popular as die sizes increase and technology sizes decrease. The complexity of integrating different types of Processing Elements (PEs) that use different communication protocols and interfaces complicates the system-level design methodology. Recent work provided a proof of concept demonstrating how a controller could be used to provide a generic system-level interface that separates the functionality of a PE from its communication protocols and makes the actual physical interconnections between modules a lesser problem. This paper summarizes how the SIMPPL model is able to implement the systemspecific requirements of an MPEG-1 video decoder and the overhead this framework incurs.
Lesley Shannon, Blair Fort, Samir Parikh, Arun Pat
Added 24 Jun 2010
Updated 24 Jun 2010
Type Conference
Year 2005
Where FPT
Authors Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow
Comments (0)
books