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2009
IEEE

Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints

9 years 2 months ago
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them allows fast design time, ease of routing, predictability of electrical parameters and good scalability. k-ary n-mesh topologies are candidate solutions for these systems, borrowed from the domain of off-chip interconnection networks. However, the on-chip integration has to deal with unique challenges at t levels of abstraction. From a technology viewpoint, interconnect reverse scaling causes critical paths to go across global links. Poor interconnect performance might also impact IP core speed depending on the synchronization mechanism at the interface. Finally, this might also conflict with the requirements that communication libraries employed in the MPSoC domain pose on the underlying interconnect fabric. This paper provides a comprehensive overview of these topics, by characterizing physical feasibility o...
Francisco Gilabert Villamón, Daniele Ludovi
Added 18 May 2010
Updated 18 May 2010
Type Conference
Year 2009
Where CISIS
Authors Francisco Gilabert Villamón, Daniele Ludovici, Simone Medardoni, Davide Bertozzi, Luca Benini, Georgi Nedeltchev Gaydadjiev
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