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IJES
2008

On-chip implementation of multiprocessor networks and switch fabrics

10 years 10 months ago
On-chip implementation of multiprocessor networks and switch fabrics
: On-chipimplementationofmultiprocessorsystemsneedstoplanarisetheinterconnect networks onto the silicon floorplan. Compared with traditional ASIC/SoC architectures, Multiprocessor Systems on Chips (MPSoC) node processors are homogeneous, and MPSoC network topologies are regular. Therefore, traditional ASIC floorplanning methodologies that perform macro placement are not suitable for MPSoC designs. We propose an automated MPSoC physical planning methodology. REGULAY can generate an optimal floorplan for different topologies under different design constraints. Compared with traditional floorplanning approaches, REGULAY shows significant advantages in reducing the total interconnect wirelength while preserving the regularity and hierarchy of the network topology.
Terry Tao Ye, Giovanni De Micheli
Added 12 Dec 2010
Updated 12 Dec 2010
Type Journal
Year 2008
Where IJES
Authors Terry Tao Ye, Giovanni De Micheli
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