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FCCM
2008
IEEE

DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs

10 years 5 months ago
DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs
We present an AES cipher implementation that is based on the BlockRAM and DSP units embedded within Xilinx’s Virtex-5 FPGAs. An iterative “basic” module outputs a 32 bit column of an AES round each clock cycle, with a
Saar Drimer, Tim Güneysu, Christof Paar
Added 29 May 2010
Updated 29 May 2010
Type Conference
Year 2008
Where FCCM
Authors Saar Drimer, Tim Güneysu, Christof Paar
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