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FPL
2005
Springer

Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs

9 years 7 months ago
Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs
Due to their layered approach, Networks-on-Chip (NoC) are a promising communication backbone in the field of heterogeneous dynamically reconfigurable systems. In this paper a future FPGA architecture is discussed having a hardwired NoC as an additional high-level routing resource. Instead of implementing on-chip interconnection with valuable reconfigurable resources, on top of this architecture, cost-efficient statically and dynamically reconfigurable systems can be built. The concept of such an FPGA is explored by means of an abstract SystemC model. This model not only implements the NoC but also permits a tile based dynamic reconfiguration. It will be shown, that this approach advances the research on operating system support for dynamic reconfiguration in a new way.
Ronald Hecht, Stephan Kubisch, Andreas Herrholtz,
Added 27 Jun 2010
Updated 27 Jun 2010
Type Conference
Year 2005
Where FPL
Authors Ronald Hecht, Stephan Kubisch, Andreas Herrholtz, Dirk Timmermann
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