FPL 2005 - PDF Preprint Papers

FPL 2005 International Conference on Field Programmable Logic and Applications

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FPL
2005
Springer

226views Hardware» more FPL 2005»

A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC

13 years 10 months ago

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A parallel MPEG-4 Simple Profile encoder for FPGA based multiprocessor System-on-Chip (SOC) is presented. The goal is a computationally scalable framework independent of platform....

Olli Lehtoranta, Erno Salminen, Ari Kulmala, Marko...

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Id	Views	Title	Status

1	226	A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC	claim
2	172	An FPGA Network Architecture for Accelerating 3DES - CBC	claim
3	165	DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices	claim
4	149	Heterogeneity Exploration for Multiple 2D Filter Designs	claim
5	144	Accelerating Molecular Dynamics Simulations With Configurable Circuits	claim
6	140	A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs	claim
7	140	A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow	claim
8	139	Mullet - A Parallel Multiplier Generator	claim
9	138	Snort Offloader: A Reconfigurable Hardware NIDS Filter	claim
10	137	Bitwise Optimised CAM for Network Intrusion Detection Systems	claim
11	136	Architecture-Adaptive Routability-Driven Placement for FPGAs	claim
12	131	An Efficient Approach to Hide the Run-Time Reconfiguration from SW Applications	claim
13	130	Communication Synthesis in a multiprocessor environment	claim
14	127	Efficient Hardware Architectures for Modular Multiplication on FPGAs	claim
15	127	Fast FPGA Placement using Space-filling Curve	claim
16	125	Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor	claim
17	122	FPGA-Aware Garbage Collection in Java	claim
18	121	Configuration Merging for Adaptive Computer Applications	claim
19	119	Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes	claim
20	119	Real-Time Feature Extraction for High Speed Networks	claim
21	115	Statistical Power Estimation for FPGA	claim
22	114	Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks	claim
23	114	Post-Placement BDD-Based Decomposition for FPGAs	claim
24	113	A Reconfigurable Perfect-Hashing Scheme for Packet Inspection	claim
25	113	Ziggurat-based Hardware Gaussian Random Number Generator	claim
26	112	Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement	claim
27	112	Hierarchical Placement for Large-scale FPAA	claim
28	111	Mutable Codesign for Embedded Protocol Processing	claim
29	110	CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools	claim
30	107	Programmable Numerical Function Generators: Architectures and Synthesis Method	claim
31	103	Low Power Domain-Specific Reconfigurable Array for Discrete Wavelet Transforms Targeting Multimedia Applications	claim
32	101	Evaluation of Ray Casting on Processor-Like Reconfigurable Architectures	claim
33	100	HAIL: A Hardware-Accelerated Algorithm for Language Identification	claim
34	100	Power and Area Optimization for Multiple Restricted Multiplication	claim
35	98	A Verilog RTL Synthesis Tool for Heterogeneous FPGAs	claim
36	98	Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow	claim
37	97	Safe PLD-based Programmable Controllers	claim
38	96	Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs	claim
39	96	FPGA PLB Evaluation using Quantified Boolean Satisfiability	claim
40	96	FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations	claim
41	96	An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform	claim
42	89	Snow 2.0 IP Core for Trusted Hardware	claim
43	89	Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC	claim
44	86	On the Reliability Evaluation of SRAM-Based FPGA Designs	claim
45	79	PGR: A Software Package for Reconfigurable Super-Computing	claim
46	79	FPGA-based implementation and comparison of recursive and iterative algorithms	claim
47	73	Defect Tolerance in Multiple-FPGA Systems	claim
48	73	Energy-Efficient NoC for Best-Effort Communication	claim
49	60	Performance Tuning of Iterative Algorithms in Signal Processing	claim

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