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FPT
2005
IEEE

Dynamic Voltage Scaling for Commercial FPGAs

8 years 11 months ago
Dynamic Voltage Scaling for Commercial FPGAs
A methodology for supporting dynamic voltage scaling (DVS) on commercial FPGAs is described. A logic delay measurement circuit (LDMC) is used to determine the speed of an inverter chain for various operating conditions at run time. A desired LDMC value, intended to match the critical path of the operating circuit plus a safety margin, is then chosen; a closed loop control scheme is used to maintain the desired LDMC value as chip temperature changes, by automatically adjusting the voltage applied to the FPGA. We describe experiments using this technique on various circuits at different clock frequencies and temperatures to demonstrate its utility and robustness. Power savings between 4% and 54% for the VINT supply are observed.
C. T. Chow, L. S. M. Tsui, Philip Heng Wai Leong,
Added 24 Jun 2010
Updated 24 Jun 2010
Type Conference
Year 2005
Where FPT
Authors C. T. Chow, L. S. M. Tsui, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton
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