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DAC
1999
ACM

Dynamically Reconfigurable Architecture for Image Processor Applications

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Dynamically Reconfigurable Architecture for Image Processor Applications
This work presents an overview of the principles that underlie the speed-up achievable by dynamic hardware reconfiguration, proposes a more precise taxonomy for the execution models for reconfigurable platforms, and demonstrates the advantage of dynamic reconfiguration in the new implementation of a neighborhood image processor, called DRIP. It achieves a realtime performance, which is 3 times faster than its pipelined nonreconfigurable version Keywords Reconfigurable architecture, image processing, FPGA
Alexandro M. S. Adário, Eduardo L. Roehe, S
Added 02 Aug 2010
Updated 02 Aug 2010
Type Conference
Year 1999
Where DAC
Authors Alexandro M. S. Adário, Eduardo L. Roehe, Sergio Bampi
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