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2010
IEEE

DynTile: Parametric tiled loop generation for parallel execution on multicore processors

9 years 9 months ago
DynTile: Parametric tiled loop generation for parallel execution on multicore processors
Abstract--Loop tiling is an important compiler transformation used for enhancing data locality and exploiting coarsegrained parallelism. Tiled codes in which tile sizes are runtime parameters--called parametrically-tiled codes--are important for empirical tuning systems like ATLAS. Some recent work has addressed the problem of generating sequential parametric tiled code. In this paper we describe DynTile, a system for transforming untiled sequential input C code containing affine imperfectly nested loops to parametrically tiled code for parallel execution on multicore processors. The effectiveness of the system is demonstrated using a number of benchmarks on an eight-core system.
Albert Hartono, Muthu Manikandan Baskaran, J. Rama
Added 13 Feb 2011
Updated 13 Feb 2011
Type Journal
Year 2010
Where IPPS
Authors Albert Hartono, Muthu Manikandan Baskaran, J. Ramanujam, Ponnuswamy Sadayappan
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