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2004
ACM

Early-stage power grid analysis for uncertain working modes

9 years 6 months ago
Early-stage power grid analysis for uncertain working modes
High performance integrated circuits are now reaching the 100-plus watt regime, and power delivery and power grid signal integrity have become critical. Analyzing the performance of the power delivery system requires knowledge of the the current drawn by the functional blocks that comprise a typical hierarchical design. However, current designs are of such complexity that it is difficult for a designer to determine what a realistic worst-case switching pattern for the various blocks would be in order to maximize noise at a specific location. This paper uses information about the power dissipation of a chip to derive an upper bound on the worst-case voltage drop at an early stage of design. An exact ILP method is first developed, followed by an effective heuristic to speed up the exact method. A circuit of 43K nodes is analyzed within 70 seconds, and the worstcase scenarios found correlate well with the results from an ILP solver. Categories and Subject Descriptors B.7.2 [Integrated...
Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
Added 30 Jun 2010
Updated 30 Jun 2010
Type Conference
Year 2004
Where ISPD
Authors Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
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