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DAC
2006
ACM

An efficient retiming algorithm under setup and hold constraints

10 years 24 days ago
An efficient retiming algorithm under setup and hold constraints
In this paper we present a new efficient algorithm for retiming sequential circuits with edge-triggered registers under both setup and hold constraints. Compared with the previous work [17], which computed the minimum clock period in O(|V|3|E|lg|V|) time, our algorithm solves the same problem in O(|V|2|E|) time. Experimental results validate the efficiency of our algorithm. Categories and Subject Descriptors B.7.2 [Hardware]: Integrated Circuits--Design Aids; J.6 [Computer-Aided Engineering]: Computer-Aided Design General Terms Algorithms, Performance, Design Keywords Retiming
Chuan Lin, Hai Zhou
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2006
Where DAC
Authors Chuan Lin, Hai Zhou
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