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DAC
2006
ACM
14 years 5 months ago
An efficient retiming algorithm under setup and hold constraints
In this paper we present a new efficient algorithm for retiming sequential circuits with edge-triggered registers under both setup and hold constraints. Compared with the previous...
Chuan Lin, Hai Zhou
ICCAD
1999
IEEE
90views Hardware» more  ICCAD 1999»
13 years 9 months ago
Marsh: min-area retiming with setup and hold constraints
This paper describes a polynomial time algorithm for min-area retiming for edge-triggered circuits to handle both setup and hold constraints. Given a circuit G and a target clock ...
Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K...
TCAD
2002
91views more  TCAD 2002»
13 years 4 months ago
Retiming and clock scheduling for digital circuit optimization
Abstract--This paper investigates the application of simultaneous retiming and clock scheduling for optimizing synchronous circuits under setup and hold constraints. Two optimizati...
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
DATE
1999
IEEE
127views Hardware» more  DATE 1999»
13 years 9 months ago
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits
This paper investigates retiming and clock skew scheduling for improving the tolerance of synchronous circuits to delay variations. It is shown that when both long and short paths...
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
ENDM
2010
67views more  ENDM 2010»
13 years 1 months ago
An exact method for the bi-objective one-machine problem with maximum lateness and unit family setup cost objectives
This paper deals with an NP-hard bi-objective one-machine problem with ready times involving maximum lateness and unit family setup cost objectives. Considering separately both ob...
Christian Artigues, Nicolas Jozefowiez, Mohamed Al...