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MICRO
2006
IEEE

Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance

13 years 4 months ago
Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance
Runahead execution improves memory latency tolerance without significantly increasing processor complexity. Unfortunately, a runahead execution processor executes significantly more instructions than a conventional processor, sometimes without providing any performance benefit, which makes it inefficient. In this article, we identify the causes of inefficiency in runahead execution and propose simple -yet effective- techniques to make a runahead processor more efficient, thereby reducing its energy consumption. The proposed efficiency techniques reduce the extra instructions executed in a runahead processor from 26.5% to 6.2% without significantly affecting the 22% performance improvement provided by runahead execution.
Onur Mutlu, Hyesoon Kim, Yale N. Patt
Added 14 Dec 2010
Updated 14 Dec 2010
Type Journal
Year 2006
Where MICRO
Authors Onur Mutlu, Hyesoon Kim, Yale N. Patt
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