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EDCC
2005
Springer

Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs

11 years 5 months ago
Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs
Abstract. Current paper proposes an efficient alternative for traditional gatelevel fault simulation. The authors explain how Structurally Synthesized Binary Decision Diagrams (SSBDD) can be used for representation, simulation and fault modeling of digital circuits. It is shown how the first phase of any fault simulation algorithm: the fault-free simulation can be accelerated using this model. Moreover, it is pointed out that simultaneous to simulation on SSBDDs, the set of potential fault locations can be significantly reduced. In addition, algorithms for deductive and concurrent fault simulation on SSBDD models are introduced in the paper. While full implementation of the new SSBDD based algorithms needs to be carried out, the paper presents experimental data revealing the advantages of the proposed data structure in the fault simulation process.
Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jut
Added 27 Jun 2010
Updated 27 Jun 2010
Type Conference
Year 2005
Where EDCC
Authors Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman
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