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ISCAS
2003
IEEE

An efficient transistor optimizer for custom circuits

9 years 3 months ago
An efficient transistor optimizer for custom circuits
We present an equation-based transistor size optimizer that minimizes delay of custom circuits. Our method uses static timing analysis to find the critical paths and numerical methods to optimize transistor sizes continuously without using simulation. Consequently, it is faster than simulation-based optimizers, and more general than standard cell optimizers. We demonstrate its efficacy and accuracy on a dynamic adder, where we achieve a 54% speed-up and final critical path delay that matches Spice within 1%.
Xiao Yan Yu, Vojin G. Oklobdzija, William W. Walke
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ISCAS
Authors Xiao Yan Yu, Vojin G. Oklobdzija, William W. Walker
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