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1999
IEEE

An Efficient VLSI Architecture Parallel Prefix Counting With Domino Logic

9 years 6 months ago
An Efficient VLSI Architecture Parallel Prefix Counting With Domino Logic
We propose an efficient reconfigurable parallel prefix counting network based on the recently-proposed technique of shift switching with domino logic, where the charge/discharge signals propagate along the switch chain producing semaphores results in a network that is fast and highly hardware-compact. The proposed architecture for prefix counting
Rong Lin, Koji Nakano, Stephan Olariu, Albert Y. Z
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where IPPS
Authors Rong Lin, Koji Nakano, Stephan Olariu, Albert Y. Zomaya
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