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2009
ACM

EINIC: an architecture for high bandwidth network I/O on multi-core processors

8 years 11 months ago
EINIC: an architecture for high bandwidth network I/O on multi-core processors
This paper proposes a new server architecture EINIC (Enhanced Integrated NIC) for multi-core processors to tackle the mismatch between network speed and host computational capacity. Similar to prior work, EINIC integrates a redesigned NIC onto a CPU. However, we extend the integrated NIC (INIC) to multicore platforms and examine its behaviors with the network receiving optimization. Additionally, by exploiting NICs proximity to CPUs, we also design an I/O-aware last level shared cache (LLC). Our I/O-aware design allows us to split the cache into an I/O cache and a general cache in a flexible way. It ameliorates cache interferences between network and non-network data. Our simulation results show that EINIC not only attacks the mismatch, but also ameliorates the cache interference. Categories and Subject Descriptors C.2.1 [Computer-Communication Networks]: Network Architecture and Design. General Terms Measurement, Performance, Design, Experiments. Keywords EINIC, Integrated NIC, Cache...
Guangdeng Liao, Laxmi N. Bhuyan, Danhua Guo, Steve
Added 16 Feb 2011
Updated 16 Feb 2011
Type Journal
Year 2009
Where ANCS
Authors Guangdeng Liao, Laxmi N. Bhuyan, Danhua Guo, Steve R. King
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