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HPCA
2011
IEEE
8 years 2 months ago
ACCESS: Smart scheduling for asymmetric cache CMPs
In current Chip-multiprocessors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primari...
Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishanka...
GLVLSI
2011
IEEE
344views VLSI» more  GLVLSI 2011»
8 years 2 months ago
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
Azam Seyedi, Adrià Armejach, Adrián ...
DATE
2011
IEEE
223views Hardware» more  DATE 2011»
8 years 2 months ago
Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...
Martin Schoeberl, Pascal Schleuniger, Wolfgang Puf...
TVLSI
2010
8 years 5 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
SIGOPS
2010
179views more  SIGOPS 2010»
8 years 5 months ago
Online cache modeling for commodity multicore processors
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
Richard West, Puneet Zaroo, Carl A. Waldspurger, X...
CAL
2010
8 years 7 months ago
SMT-Directory: Efficient Load-Load Ordering for SMT
Memory models like SC, TSO, and PC enforce load-load ordering, requiring that loads from any single thread appear to occur in program order to all other threads. Out-of-order execu...
A. Hilton, A. Roth
CAL
2010
8 years 7 months ago
A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors
This paper describes dynamic pressure-aware associative placement (DPAP), a novel distributed cache management scheme for large-scale chip multiprocessors. Our work is motivated by...
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem
IEEEPACT
2009
IEEE
8 years 8 months ago
FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery
Abstract--Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current...
Marc Lupon, Grigorios Magklis, Antonio Gonzá...
IEEEPACT
2009
IEEE
8 years 8 months ago
Cache Sharing Management for Performance Fairness in Chip Multiprocessors
Resource sharing can cause unfair and unpredictable performance of concurrently executing applications in Chip-Multiprocessors (CMP). The shared last-level cache is one of the mos...
Xing Zhou, Wenguang Chen, Weimin Zheng
ICPP
2009
IEEE
8 years 8 months ago
Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this c...
Matteo Monchiero, Ramon Canal, Antonio Gonzá...
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