Enabling energy efficiency in via-patterned gate array devices

10 years 2 months ago
Enabling energy efficiency in via-patterned gate array devices
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architectures. These architectures represent a departure from traditional standard-cell-based ASIC designs in favor of techniques which present more physical and structural regularity. If structured ASICs are to become a viable alternative to standard cells, they must deliver performance and energy efficiency which is competitive with standard-cell-based design techniques. This paper focuses on one family of structured ASICs known as via-patterned gate arrays, or VPGAs. In this paper, we present circuit structures and power optimization algorithms which can be applied to VPGA chips in an effort to reduce their operational power dissipation. Categories and Subject Descriptors B.6.3 [Design Aids]: Optimization; B.7.1 [Types and Design Styles]: Gate Arrays General Terms Design, Performance, Algorithms Keywords Structured AS...
R. Reed Taylor, Herman Schmit
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2004
Where DAC
Authors R. Reed Taylor, Herman Schmit
Comments (0)