7 search results - page 1 / 2 » Enabling energy efficiency in via-patterned gate array devic... |
DAC
2004
ACM
13 years 8 months ago
2004
ACM
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architecture...
FPL
2000
Springer
13 years 8 months ago
2000
Springer
Abstract. This paper presents an innovative architecture for a reconfigurable device that allows single cycle context switching and single cycle random access to the unified on-chi...
TVLSI
2008
13 years 4 months ago
2008
A new set of programmable elements (PEs) using a new non-volatile device for use with routing switches and logical elements within a field-programmable gate array (FPGA) is describ...
CDES
2008
13 years 6 months ago
2008
- The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, prac...
BMCBI
2008
13 years 4 months ago
2008
Background: This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomic...