Sciweavers

Share
CODES
2005
IEEE

Enhanced code density of embedded CISC processors with echo technology

9 years 9 months ago
Enhanced code density of embedded CISC processors with echo technology
Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even at the cost of significant performance loss. In this paper, we develop an algorithm that utilizes a set of novel variable length Echo instructions and evaluate its effectiveness for IA32 binaries. Our experiments show that IA32 processor equipped with Echo instructions is capable of achieving a similar code density as the THUMB extension in the ARM instruction set with significantly lower performance penalty. Categories and Subject Descriptors D.3.4 [Programming languages] Processors – Compilers, Optimization
Youfeng Wu, Mauricio Breternitz Jr., Herbert H. J.
Added 24 Jun 2010
Updated 24 Jun 2010
Type Conference
Year 2005
Where CODES
Authors Youfeng Wu, Mauricio Breternitz Jr., Herbert H. J. Hum, Ramesh V. Peri, Jay Pickett
Comments (0)
books