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DAC
2007
ACM

Enhancing FPGA Performance for Arithmetic Circuits

11 years 2 months ago
Enhancing FPGA Performance for Arithmetic Circuits
FPGAs offer flexibility and cost-effectiveness that ASICs cannot match; however, their performance is quite poor in comparison, especially for arithmetic dominated circuits. To address this issue, this paper introduces a novel reconfigurable lattice built from counters rather than look-up tables that can effectively accelerate the arithmetic portions of a circuit. We intend to integrate this novel lattice onto the same die as an FPGA. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles ? gate arrays; B.2.4 [Arithmetic and Logic Structures]: High Speed Arithmetic ? algorithms, cost/performance. General Terms Algorithms, Performance, Design. Keywords Field Programmable Gate Array (FPGA), Field Programmable Counter Array (FPCA) Look-up Table (LUT), Compressor Tree.
Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Par
Added 12 Nov 2009
Updated 12 Nov 2009
Type Conference
Year 2007
Where DAC
Authors Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Parandeh-Afshar
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